1. Field of Invention
This invention relates to FIFO queues and, more particularly, to synchronization of FIFO data transfers between two clock domains.
2. Description of Related Art
In digital electronic systems, a clock of some sort is usually present to provide a timing reference for dynamic processes. In such systems, the output of the clock is generally a periodic waveform, alternating between two voltage levels. Discrete states within the system are associated with clock transitions. Thus, a synchronous logic device may change from one state to another only on a rising or falling edge of the clock. The transfer of digital data is also frequently governed by a clock. For example, a peripheral device in a personal computer may exchange data with the main processor using a high-speed bus, such as the PCI bus, in which a clock is employed to synchronize read/write operations.
It is sometimes necessary to transfer data between two systems having different clocks. One means of accomplishing this is to use a first-in first-out (FIFO) buffer. Data are typically received at the FIFO input and propagate through the FIFO at each clock transition, eventually reaching the output. The FIFO derives its name from the fact that the data emerge from the FIFO in the same order in which they enter (therefore, a FIFO is a type of queue). A FIFO may employ different clocks for reading and writing data. This can be very useful for “burst mode” data transfers. For example, suppose it is necessary to record a transient event using a high-speed digital video camera, and then transfer the data to a computer. This presents a problem, since the camera may collect samples at a rate much higher than the computer can receive them. A dual-clock FIFO may be used to buffer the data however. The samples can be entered into the FIFO by the camera's sample clock, and subsequently read out by the slower computer clock. As long as the FIFO is fast enough to keep up with the camera and deep enough to hold all the samples, there is no data loss.
It is often advantageous to include tag bits along with the data in the FIFO entries. These tag bits may be used as flags to denote the type of transaction for which the data is intended. For example, individual bits can be used to distinguish a read or write operation, or to indicate the source of the data. Tagging can facilitate data transfer, since less processing is required at the receiving end to ascertain the nature of the transfer. Note that the width of each FIFO entry (i.e., number of bits) must include the tab bits as well as the data. For example, each FIFO entry might be 10 bits wide, to accommodate 8 bit data words with 2 tag bits.
In some situations, data are continuously written to and read from a dual clock FIFO. It is essential in such cases to known which locations in the FIFO contain valid data. When power is first applied, the FIFO is filled with random data—so every entry is invalid. Thereafter, a valid entry is created each time a new value is clocked into the FIFO; the entry becomes invalid when its contents are clocked out. Typically, read and write pointers store the location of the oldest and most recent valid entries in the FIFO.
To reduce latency in a dual clock FIFO system, it is desirable to be able to determine the status of the tag bits belonging to valid FIFO entries prior to actually reading the entries. This requires a means for selectively testing tag bits in the valid entries, while ignoring the invalid entries. The circuitry to perform this function must be relatively simple (so it can be readily implemented in an integrated circuit) and capable of high-speed operation (so its use does not compromise FIFO throughput). A further requirement is that the circuitry operates across two different clock domains.